### IC 74153 DATASHEET PDF

TL F –1. Order Number DMQB FMQB DMJ. DMW or DMN. See NS Package Number J16A N16E or W16A. Function Table. datasheet, pdf, data sheet, datasheet, data sheet, pdf, National Semiconductor, Dual 4-Line to 1-Line Data Selectors/Multiplexers. The LSTTL/MSI SN54/74LS is a very high speed Dual 4-Input. Multiplexer with common select inputs and individual enable inputs for each section.

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If integrated logical doors are used, one obtains the circuit represented on figure In addition datzsheet the commutation of several logical signals, the multiplexer can be used to replace a network. The example which follows 74513 clarify the procedure. The stitching and the logic diagram of this circuit are given on 7413 41, while figure 42 gives its truth table.

The not selected exits position with state 1. Return to the synopsis. It now remains to carry the selected entries at the levels indicated in the last column. The diagram symbolic system and the mechanical equivalent of a demultiplexer with 2 ways are presented at figure According to what was known as before, the four switches are connected to the four entries of order D, C, B, A of the multiplexer.

Let us carry the entry of validation to state 0: One has four switches being able to be connected either to the supply voltage, or with the mass and one wants to know so at least dagasheet switches are closed again on the positive tension of food.

### Datasheet pdf – Dual 4-Line to 1-Line Data Selectors/Multiplexers – National Semiconductor

How to make a site? We know that the majority of the decoders have their active exits at state 0 and their entry of active validation to state 0. It is noticed that the binary number formed by the state of the entries of selection B and A gives the decimal index of the exit concerned. 47153

Electronic forum and Infos. The integrated circuit 74LS contains two demultiplexers with 4 ways. We will see that the same function can be obtained with a single multiplexer at sixteen entries.

## (PDF) 74153 Datasheet download

For each combination of the entries of order, one defers in the column of the exit the state that this one must take.

The integrated circuit contains two multiplexers with 4 ways at entries of selection A and B communes. On the other hand, entry 3 on the level Htherefore is connected to the positive tension. Since all the combinations of the entries A, B, C and D are present in this equation, we can fulfill with this multiplexer any switching function comprising the same number of entries, that is to say 4.

## National Semiconductor

The stitching and the logic diagram of this integrated circuit are given on figure 32, while 7413 33 gives its truth table. Forms maths Geometry Physics 1.

The circuit which results from it is deferred on figure One does not find a demultiplexer with 2 ways integrated. The combinative circuit which fulfills the function of the demultiplexer with 2 ways must thus correspond to the truth table of figure In this chapter, we will examine the demultiplexers which are circuits whose function iv opposite among that of the multiplexers.

This one, carried to the state 1force the exit of the multiplexer corresponding to state 0 independently of the state of the other entries.

Static page of welcome. Figure 43 illustrates how one passes from a decoder to a demultiplexer. Electronic forum and Poem. If one has the integrated circuitone can carry out the circuit of figure The exit S with for the equation: To determine how to connect the sixteen inputs, it is enough to follow the described procedure and to build a table with sixteen lines like that of figure Thus to use a decoder out of demultiplexer, the entry of validation becomes the input and the entries of the decoder become the entries of ordering of the demultiplexer.

This is made possible because the equation of the exit of a multiplexer reveals all the possible combinations of the entries of order. Click here for the following lesson or in the synopsis envisaged to this end.

### Datasheet(PDF) – National Semiconductor (TI)

The two groupings and D give us the following equation icc S1: In short, the logical data present on the entry of validation is acicular towards the exit selected by the entries of the decoder. One realizes that it is necessary to employ several types of doors, of the doors OR with 3 entriesa door OR at 2 entries and a door AND 4 entries.

The expressions and lead us to the logic diagram of figure High of page Preceding page Following page.

To know how to position the other entries, one draws up a table with all the combinations of the entries of order. This one indeed requires at least three integrated circuits: Information, present on the input, is acicular towards the exit selected by the state of the entries of order.

The next theory will treat memories.